ISA Verification, Instruction Semantics, Hardware Proofs, Architecture Validation

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One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon
riscv.org·16h
🧲RISC-V Preservation
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Lessons from Formally Verified Deployed Software Systems (Extended version)
arxiv.org·1d
⚖️Verification Calculi
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Hint-Based SMT Proof Reconstruction
arxiv.org·7h
🧮SMT Solvers
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Multi-Modal Program Verification in Velvet
proofsandintuitions.net·1d·
Discuss: Hacker News
⚖️Verification Calculi
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Recap of ELISA Project at Linux Plumbers Conference: Tokyo, Japan 2025
elisa.tech·17h
🔍eBPF
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BPF Verifier State Pruning: Timeline
pchaigno.github.io·2d
🛡️Archive Verification
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Can We Build an NX Bit for LLMs
bogdandeac.com·1d·
Discuss: Hacker News
🖥️Modern Terminals
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Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V Extension
semiwiki.com·1d
📊RISC-V Vectors
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I am performing chipset-level repair on a Biostar B460GTA Rev 5.0 motherboard and I need help.
forums.anandtech.com·1d
Circuit Archaeology
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Making a Language
thunderseethe.dev·13h
🛠Language Design
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VCP v1.1: Cryptographic Audit Trails for AI Trading Systems (EU AI Act Ready)
dev.to·2h·
Discuss: DEV
🌳Archive Merkle Trees
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Issue 508
haskellweekly.news·57m
🔗Functional Compilers
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RISC-V and Post-Quantum Cryptography
fprox.substack.com·2d·
Discuss: Substack
🔐Quantum Security
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High-Performance Industrial Control Platform Using MST3576
hackster.io·3d
⚙️RISC-V Microcode
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Building Your Own Efficient uint128 in C++
solidean.com·1d·
🧮Algebraic Datatypes
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In Praise of APL (1977)
jsoftware.com·3h·
Discuss: Hacker News
📊APL Heritage
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Every Mini PC & SFF Hardware Announced at CES 2026
williamlam.com·20h
🖥️Terminal Renaissance
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Introducing VulHunt: A High-Level Look at Binary Vulnerability Detection
binarly.io·1d
🔬Binary Analysis
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Soundness bugs in Rust libraries: can't live with 'em, can't live without 'em
docs.rs·20h·
Discuss: Hacker News
🔒Type Safety
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CodeSOD: Well Timed Double Checking
thedailywtf.com·2d
🧪Binary Fuzzing
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